Field of the Invention
The invention relates to a programmable logic array having the characteristics:
(a) the array includes configurable logic cells, which are disposed in lines and columns; PA0 (b) the array includes conductor tracks, which can be connected to one another through switching elements; PA0 (c) each of the logic cells has signal inputs, control inputs, and at least one signal output; PA0 (d) the signal output of each logic cell can be connected to at least one of the signal inputs of at least a further one of the logic cells through the switching elements and conductor tracks; and PA0 (e) the signal output of each logic cell is preceded by an output driver circuit, which is connected to one of the control inputs.
A programmable logic array is known, for instance from an article entitled "Architecture of Field-Programmable Gate Arrays: The Effects of Logic Block Functionality on Area Efficiency" by J. Rose et al, in IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, Oct. 1990. Such an array contains a plurality of logic cells, which are disposed regularly, for instance in lines and columns. The logic cells have a plurality of input signal terminals, at least one output signal terminal, and terminals for control signals. By way of example, they include a memory element and circuit means with which a combinatorial logic function can be achieved. The circuit means and the memory elements can be connected to one another through a number of possible predetermined signal paths. One output of the memory element may be fed back to its input, either directly or through the circuit means. The output of the logic cell can be connected to the output of the memory element or to one output of the circuit means. The input of the memory element can also be connected directly to an input signal terminal. In the connection paths mentioned, multiplexing devices are incorporated, with which one of the possible signal paths is selected. In order to configure the logic cell, control signals through which the multiplexing devices are controlled are applied to the control inputs.
Connecting lines and circuit elements for electrically connecting the connecting lines are also present. The circuit elements are controllable in such a way that two intersecting connecting lines can be electrically connected with one another by them. In that way, the output of one logic cell is connected to an input of a further logic cell. Through the use of the configuration of a logic cell by means of the control signals and through the connection of logic cells with one another, a switch mechanism, that is a logical linkage, in which states are stored in memory, is achieved.
The signal delay time along the connecting lines between interconnected logic cells is known to rise with increasing line length. Therefore, long connections reduce the processing speed of the switch mechanism made with the configuration. Any statement about the signal transit time is accordingly possible only after the logic gate functions that realize the switching mechanism have been placed in various cells and they have been connected.